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ASYNCHRONOUS VLSI CHIPS @ CALTECH
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The Caltech MiniMIPS is an asynchronous MIPS R3000 designed between 1995 and 1998. The R3000 is a "classic" RISC processor: It consists of a full 32-bit RISC CPU, and a memory management unit. The CPU has 32 32-bit general-purpose registers, a program counter, and two special-purpose registers for multiplication and division. It has two operating modes, user and kernel. Branches have a single delay-slot. There are 2 4KB caches: an instruction cache, and a direct-mapped write-through data cache. Cache lines are one-word long, and refills are 4-word blocks. Exceptions (interrupts) are precise.

The first prototype misses the TLB (address translation mechanism) which we found much too complicated, the partial-word memory operations, and some cache instructions. A full-custom hand layout, it was fabricated in HP's 0.6 µm CMOS process via MOSIS (3-metal, 1-poly, linear cap, silicide block, n-well, 3.3V). The area is 8 by 14 sq mm, and the transistor count is 2M (1.25M for caches).

From extensive SPICE simulations, the performance should have been 280 MIPS at 3.3V and 75o. But this first prototype didn't achieve these performances. All chips were found functional except one whose package was defective. The test performance on small programs are as follows.

180 MIPS and 4W at 3.3V and 25o

100 MIPS and 850mW at 2.0V and 25o

60 MIPS and 220mW at 1.5V and 25o

The performance figures running Dhrystone are 185 MHz at 3.3V on the pins and at room temperature, which gives a performance figure of about 165 VAX-MIPS.

We expected 280 MHz, we got about 180 MHZ. A performance loss of 20% was caused by the HP process. This particular run was slow, which brought the performance down to 220 MHZ. The other 20% performance loss, which brings us down to the observed 180 MHz, was caused by a layout error: a long polysilicon wire was forgotten in a single unit, and was unnoticed in SPICE simulations because resistance in long wires was not modeled. (We were relying on good layout discipline.)

In spite of this slight disappointment, the performance obtained on this very first prototype is excellent. The performance of the MiniMIPS is about two-and-a-half times better than that of commercial microprocessors of the same type and in equivalent technology.

For more details about the MiniMIPS, see the original paper The Design of an Asynchronous MIPS R3000 Microprocessor, and the report Speed and Energy Performance of an Asynchronous MIPS R3000 Microprocessor. The CAM, the MiniMIPS, and the Lutonium--an ultra low power asynchronous 8051 microcontroller also designed by our group--are presented together in the paper Three Generations of Asynchronous Microprocessors.


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Mailing Address: Alain Martin, Department of Computer Science, Caltech 256-80, Pasadena CA 91125, USA.
This research is supported by the National Science Foundation.
Last Modified: 07 Dec 2006