Reliable Minimum Energy CMOS Circuit Design. Sean Keller, Siddarth S. Bhargav, Chris Moore, Alain J. Martin. Vari11 2nd European Workshop on CMOS Variability, 2011 [PDF]

Asynchronous Logic for High Variability Nano-CMOS. Alain J. Martin. Proc. IEEE Conference on Electronic Circuits and Systems, 2009 [PS]

A Soft-error-tolerant Arbiter. Wonjin Jang and Alain J. Martin. In preparation

A Necessary and Sufficient Timing Assumption for Speed-Independent Circuits. Sean Keller, Michael Katelman, Alain J. Martin. Proc. 15th IEEE International Symposium on Asynchronous Circuits & Systems (ASYNC 2009), May 2009 [PDF]

Asynchronous Nano-electronics: Preliminary Investigation. Alain J. Martin and Piyush Prakash. in: Proc. 14th IEEE International Symposium on Asynchronous Circuits & Systems (ASYNC 2008), April 2008 [PDF]

A Soft-error tolerant Asynchronous Microcontroller. Wonjin Jang, and Alain J. Martin. 13th NASA Symposium on VLSI Design, June 2007. [PDF]

Can asynchronous techniques help the SoC designer?. Alain J. Martin. Proc. IFIP Internal Conference of Very Large Scale Integration and VLSI-SoC, October 2006 [PDF]

Asynchronous techniques for system-on-chip design. Alain J. Martin and Mika Nyström. Proceedings of the IEEE Volume 94, Issue 6:1089 - 1120, June 2006. [PDF]

Slack Matching Quasi Delay-Insensitive Circuits . Piyush Prakash, and Alain J. Martin. Proc. 12th IEEE International Symposium on Asynchronous Systems & Circuits (ASYNC), 13-15 March 2006. [PDF]

Soft-error tolerant Asynchronous FPGA. Wonjin Jang, and Alain J. Martin. Fast Abstract, Dependable System and Network 2005 , June 2005. [PDF]

Soft-error Robustness in QDI Circuits. Wonjin Jang, and Alain J. Martin. Workshop on System Effects of Logical Soft Errors - SELSE 1, 05-06 April 2005. [PDF]

SEU-tolerant QDI Circuits. Wonjin Jang and Alain J. Martin. Proc. 11th IEEE International Symposium on Asynchronous Systems & Circuits (ASYNC), 14-16 March 2005. [PDF]

Design Rules for Non-Atomic Implementations of PRS. Karl Papadantonakis. Caltech Technical Report, 2005. [PDF]

A Pipelined Asynchronous Cache System. Mika Nyström, Andrew Lines, and Alain J. Martin. Caltech Technical Report, 2003, revised 2005. [PDF]

CAST: Caltech Asynchronous Synthesis Tools. Alain J. Martin & Mika Nyström. Proc. of Fourth Asynchronous Circuit Design Working Group Workshop, Turku, Finland. June 2004.

An Eight-bit Divider Implemented in Asynchronous Pulse Logic. Mika Nyström, Elaine Ou, and Alain J. Martin. Proc. 10th IEEE International Symposium on Asynchronous Systems & Circuits (ASYNC), 19-23 April 2004. [PS]

A Failure-Free Synchronizer. Mika Nyström and Alain J. Martin. 2002. [PDF]

An Architecture for Asynchronous FPGAs. Catherine G. Wong, Alain J. Martin, and Peter Thomas. Proc. IEEE International Conference on Field-Programmable Technology (FPT), December 2003. [PS]

Three Generations of Asynchronous Microprocessors. Alain J. Martin, Mika Nyström and Catherine G. Wong. IEEE Design & Test of Computers, special issue on Clockless VLSI Design, November/December 2003. [PDF]

High-Level Synthesis of Asynchronous Systems by Data-Driven Decomposition. Catherine G. Wong and Alain J. Martin. Proc. 40th Design Automation Conference (DAC), June 2003. [PDF]

The Lutonium: A Sub-Nanojoule Asynchronous 8051 Microcontroller. Alain J. Martin, Mika Nyström, Karl Papadantonakis, Paul I. Penzes, Piyush Prakash, Catherine G. Wong, Jonathan Chang, Kevin S. Ko, Benjamin Lee, Elaine Ou, James Pugh, Eino-Ville Talvala, James T. Tong, Ahmet Tura. Proc. 9th IEEE International Symposium on Asynchronous Systems & Circuits (ASYNC), May 2003. [PS]

ROMantic: Generation and Optimization of Quasi Delay-Insensitive Read-Only Memories. Mika Nyström, Elaine Ou, Alain J. Martin. Caltech CS Technical Report, Nov. 2002. [PDF]

Tutorial: Asynchronous Microprocessor Design. Alain J. Martin, Mika Nyström and Catherine G. Wong. MICRO-35, November 18, 2002, Istanbul, Turkey.

Crossing the Synchronous-Asynchronous Divide. Mika Nyström and Alain J. Martin. Workshop on Complexity-Effective Design, 2002. [PS]

Transistor Sizing of Energy-Delay-Efficient Circuits. Paul Penzes, Mika Nyström and Alain J. Martin. 10th TAU Workshop, 2002. [PS]

Energy-Delay Efficiency of VLSI Computations. Paul Penzes and Alain J. Martin. 12th Great Lakes Symposium on VLSI, 2002. [PS]

An Energy Estimation Method for Asynchronous Circuits with Application to an Asynchronous Microprocessor. Paul Penzes and Alain J. Martin. Design Automation and Test in Europe (DATE), 2002. [PS]

Asynchronous Pulse Logic Mika Nyström and Alain J. Martin. Boston: Kluwer Academic Publishers, 2001. [Book]

Speed and Energy Performance of an Asynchronous MIPS R3000 Microprocessor Alain J. Martin, Mika Nyström, Paul Penzes, and Catherine Wong. June 2001. [ CSTR:2001.012 ]

ET2: A Metric For Time and Energy Efficiency of Computation. Alain J. Martin, Mika Nyström, and Paul Penzes. Power-Aware Computing, R.Melhem and R.Graybill ed., Kluwer Academic Publishers, 2001. [CSTR:2001.007]

Data-driven Process Decomposition For the Synthesis of Asynchronous Circuits. Catherine G. Wong and Alain J. Martin. Proc. IEEE Conference on Electronic Circuits and Systems, 2001 [PS]

Global and Local Properties of Asynchronous Circuits Optimized for Energy Efficiency. Paul Penzes and Alain J. Martin. IEEE Workshop on Power Management for Real-time and Embedded Systems, 2001. [PS | CSTR:2002.002 ]

Precise Exceptions and Interrupts in Asynchronous Processors. Rajit Manohar, Mika Nystrröm, and Alain J. Martin. Proc. 21th Conference on Advanced Research in VLSI, IEEE Computer Society Press, March 2001. [PS]

Towards an Energy Complexity of Computation . Alain J. Martin. Information Processing Letters, 77, 181-187, Elsevier, 2001. [PDF]

An Asynchronous Approach to Energy-efficient Computing and Communication. Alain J. Martin. Proc. SSGRR 2000, International Conference on Advances in Infrastructure for Electronic Business, Science, and Education on the Internet, August 2000. [PS]

Projection: A Synthesis Technique for Concurrent Systems. Rajit Manohar, Tak-Kwan Lee, and Alain J. Martin. Proc. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems, April 1999. [PS]

Remarks on Low-power Advantages of Asynchronous Circuits. Alain J. Martin. ESSCIRC'98: Low-Power Systems on a Chip, September 1998. [PS]

Slack Elasticity in Concurrent Computing. Rajit Manohar and Alain J. Martin. Proc. 4th International Conference on the Mathematics of Program Construction, Lecture Notes in Computer Science 1422, J. Jeuring ed., 272-285, Springer Verlag, 1998. [PS]

Pipeline Mutual Exclusion and the Design of an Asynchronous Microprocessor. Rajit Manohar and Alain J. Martin. Caltech Technical Report, 1997. [PS]

A Summary of the MIPS paper in Japanese can be found in Monthly Electronics Magazine, 8, 72-74, 1988.

The Design of an Asynchronous MIPS R3000 Microprocessor. Alain J. Martin, Andrew Lines, Rajit Manohar, Mika Nyström, Paul Penzes, Robert Southworth, Uri Cummings and Tak Kwan Lee. Proc. 17th Conference on Advanced Research in VLSI, 164-181, IEEE Computer Society Press, 1997. [PS]

A Program Transformation Approach to Asynchronous VLSI Design. Alain J. Martin. NATO ASI Series, Deductive Program Design, M. Broy ed., Springer Verlag, 1996. [PS]

The Energy and Entropy of VLSI Computations. Jose A. Tierno, Rajit Manohar, and Alain J. Martin. Async96 Second International Symposium on Advanced Research in Asynchronous Circuits and Systems, March 1996. [PS]

Quasi-Delay Insensitive Circuits are Turing-Complete. Rajit Manohar and Alain J. Martin. Invited paper, Async96 Second International Symposium on Advanced Research in Asynchronous Circuits and Systems, March 1996. [Abstract | PS | CS-TR-95-11 ]

An Action System Specification of the Caltech Asynchronous Microprocessor. R.J.R. Back, A.J. Martin, and K.Sere. Proc. 3rd International Conference on the Mathematics of Program Construction, Lecture Notes in Computer Science 947, B. Moller ed., 159-179, Springer-Verlag, 1995. Republished in Science of Computer Programming 26, Elsevier, 1996. [PS]

Extended Event-Rule Systems and Performance Analysis of Asynchronous Systems. Tak Kwan Lee and Alain J. Martin. TAU95 ACM/SIGDA International Workshop on Timing Issues in the Specification and Synthesis of Digital System, November 1995.

Low-Energy Asynchronous Memory Design. Jose A. Tierno and Alain J. Martin. Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, 176-185, IEEE Computer Society Press, November 1994. [Abstract | CS-TR-94-21]

An Asynchronous Pipeline Lattice-structure Filter. U.V. Cummings, A.M. Lines, and A.J. Martin. Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, 126-133, IEEE Computer Society Press, 1994. [PS]

Robustness Issues in Asynchronous VLSI Techniques. Alain J. MArtin. Proc. International Symposium on Fault-Tolerant Computing (FTCS-24), 94(128), June 1994. [PS]

A 100MIPS Asynchronous Microprocessor in Gallium Arsenide. Jose A. Tierno, Alain J. Martin, Drazen Borkovic, and Tak-Kwan Lee. IEEE Design & Test of Computers, 11(2), 43-49, 1994. [PDF]

An Asynchronous Microprocessor in Gallium Arsenide. Jose A. Tierno, Alain J. Martin, Drazen Borkovic, and Tak-Kwan Lee. IFIP Workshop on Logic and Architecture Synthesis, 1994. [Abstract | PS | PDF | CS-TR-93-38 ]

Synthesis of Asynchronous VLSI Circuits. Alain J. Martin. (A survey of the synthesis method as of 1991) [CS-TR-93-28]

Design of a Delay-Insensitive Multiply-Accumulate Unit. C.D. Nielsen and A.J. Martin. Proc. 26th Annual Hawaii International Conference on System Sciences, 379-388, IEEE Computer Society Press, Januray 1993. Republished in Integration, 15(3), 291-311, 1993. [CS-TR-92-03]

Translating Concurrent Programs into VLSI Chips. Alain J. Martin. Invited Paper, Proc. conference Parallel Algorithms and Languages Europe (PARLE 92), Vol. 1, 1992. Lecture Notes in Computer Science 605, 515-532, Springer-Verlag, 1992.

Tomorrow's Digital Hardware will be Asynchronous and Verified. Alain J. Martin. Invited paper, Information Processing 92, (Proc. IFIP Congress 1992), 684-695, Vol. 1, 1992. [Abstract | PS | CS-TR-93-26]

Asynchronous Datapaths and the Design of an Asynchronous Adder. Alain J. Martin. Invited paper, Formal Methods in System Design, 1(1), Kluwer, 1992. [PS | CS-TR-91-08]

Testing Delay-Insensitive Circuits. Alain J. Martin and Pieter J. Hazewindus. Proc. 1991 University of Santa Cruz Conference on Advanced Research in VLSI, ed. C.H. Sequin, 118-132, MIT Press, 1991. [Abstract | PS | CS-TR-90-17]

Performance Analysis and Optimization of Asynchronous Circuits. Steven M. Burns and Alain J. Martin. Proc. 1991 University of Santa Cruz Conference on Advanced Research in VLSI, ed. C.H. Sequin, 71-86, MIT Press, 1991. [Abstract | PS | PDF] | CS-TR-90-18 ]

A Synthesis Method for Delay-Insensitive VLSI Circuits. Alain J. Martin. Invited paper, Formal Methods for VLSI Design, ed. J. Straunstrup, 237-283, Elsevier, 1990.

The Limitations to Delay-Insensitivity in Asynchronous Circuits. Alain J. Martin. Sixth MIT Conference on Advanced Research in VLSI, ed. W.J.Dally, 263-278, MIT Press, 1990. [CS-TR-90-02 ]

Asynchronous Circuits for Token-Ring Mutual Exclusion. Alain J. Martin. [PS | CS-TR-90-09 ]

Distributed Sorting H. Peter Hofstee, Alain J. Martin, Jan L.A. van de Snepscheut. Science of Computer Programming. 15(2-3):119-133, 1990. [CS-TR-90-06]

The First Asynchronous Microprocessor: The Test Results. A.J. Martin, S.M. Burns, T.K. Lee, D. Borkovic, and P.J. Hazewindus. Computer Architecture News, 17(4), 95-110, June 1989. [CS-TR-89-06]

An Algorithm for Transitive Reduction of an Acyclic Graph. D. Gries, A.J. Martin, J. L. A. van de Snepscheut, J. T. Udding. Science of Computer Programming, North-Holland, 12(2): 151-155, 1989.

Design of Synchronization Algorithms. A.J. Martin and J.L.A. van de Snepscheut. in: M. Broy ed., Constructive Methods in Computer Science, Springer, Berlin Heidelberg, 447-478, 1989.

The Design of an Asynchronous Microprocessor. A.J. Martin, S.M. Burns, T.K. Lee, D. Borkovic, and P.J. Hazewindus. ARVLSI: Decennial Caltech Conference on VLSI, ed. C.L. Seitz, 351-373, MIT Press, 1989. [CS-TR-89-02 ]

A Message-passing Model For Highly Concurrent Computation. A.J. Martin. Third Conference on Hypercube Concurrent Computers and Applications: Architecture, Software, Computer Systems, and General Issues - Volume 1 , ACM New York, NY, 520-527, 1988. [PDF]

The architecture and programming of the Ametek series 2010 multicomputer. C.L.Seitz, W.C. Athas, C.M. Flaig, A.J. Martin, J. Seizovic, C.S. Steele, W-K. Su. Third Conference on Hypercube Concurrent Computers and Applications: Architecture, Software, Computer Systems, and General Issues - Volume 1 , ACM New York, NY, 33-37, 1988. [PDF]

Synthesis of Self-timed Circuits by Program Transformation. Steven M. Burns and Alain J. Martin. The Fusion of Hardware Design and Verification, ed. G.J. Milne, 99-116, Elsevier, 1988. [PS | PDF | 5253:TR:87 ]

VLSI Implementation of Communication with Message-passing Caltech Computer Science Technical Report 5245:TR:87.

Syntax-directed Translation of Concurrent Programs into Self-timed Circuits. Steven M. Burns and Alain J. Martin. Proc. Fifth MIT Conference on Advanced Research in VLSI, 35-50, MIT Press, 1988. [PS | PDF | CS-TR-88-14]

Formal Program Transformations for VLSI Circuits Synthesis. Alain J. Martin. Formal Developments of Programs and Proofs, UT Year of Programming Series (1987), ed. E.W. Dijkstra, 59-80, Addison-Wesley(1989). Caltech Computer Science Technical Report 5255TR:87.[5255TR:87]

A Synthesis Method for Self-timed VLSI Circuits. Alain J. Martin. Proc.1987 IEEE International Conference on Computer Design (ICCD 87), 224-229, October 1987 (Best Paper Award). [5256:TR:87]

Programming in VLSI: From Communicating Processes to Self-timed VLSI Circuits. Alain J. Martin. Proc. UT Year of Programming Institute on Concurrent Programming, March 1987, Addison-Wesley(1990). Caltech Computer Science Technical Report. [CS-TR-89-01]

The Sync Model: a Parallel Execution Method for Logic Programming. Peggy Li and Alain J. Martin. Proc. SLP'86, Third IEEE Symposium on Logic Programming, Sept. 1986. [5221:TR:86]

Compiling Communicating Processes into Delay-insensitive VLSI-circuits. Alain J. Martin. Distributed Computing, 1(4), 226-234, 1986. [5210:TR:86]

Self-timed FIFO: an Exercise in Compiling Programs into Circuits. Alain J. Martin. From HDL Description to Guaranteed Correct Circuit Design, ed. D. Borrione, 133-153, Elsevier, 1986. [5211:TR:86]

On Seitz' Arbiter Alain J. Martin. Caltech Computer Science Technical Report, June 1985. [5212:TR:86]

Distributed Mutual Exclusion on a Ring of Processes. Alain J. Martin. Science of Computer Programming, Vol.5, 3, October 1985. [5080:TR:83]

A Delay-insensitive Fair Arbiter. Alain J. Martin. June 1985. [5193:TR:85]

The Design of a Self-timed Circuit for Distributed Mutual Exclusion. Alain J. Martin. Proc. Chapel Hill Conference on VLSI, ed. H. Fuchs, 245-260, Computer Science Press, May 1985. [5097:TR:83]

The Probe: An Addition to Communication Primitives. Alain J. Martin. Information Processing Letters, 20(3), 125-130, 1985. [5124:TR:84]

A New Generalization of Dekker's Algorithm for Mutual Exclusion. Alain J. Martin. Information Processing Letters, 23(6): 295-297, 1986. [5195:TR:85]

The Design of a Self-timed Circuit for Distributed Mutual Exclusion. Proc. Chapel Hill Conf. on VLSI, 245-259, May 1985. [5097:TR:83]

Lecture Notes on Procedures. Alain J. Martin and Martin Rem. [5213:TR:86]

Fair Mutual Exclusion with Unfair P and V Operations. Alain J. Martin and Jerry R. Burch. Information Processing Letters, 21(2): 97-100, 1985. [5148:TR:84]

A Presentation of the Fibonacci Algorithm. Alain J. Martin and Martin Rem. Information Processing Letters, 19(2): 67--68, 1984.

The Sneptree---A Versatile Interconnection Network. Alain J. Martin and Peggy Li, Sept. 1984. [5194:TR:85]

A General Proof Rule for Procedures in Predicate Transformer Semantics. Alain J. Martin. Acta Informatica, 20, 301--313, 1983. [5075:TR:83]

Parallel Programs. J.L.W. Kessels and A.J. Martin. Philips Technical Review, 40, Nr.8/9, 254-260, 1982

The Torus: An Exercise in Constructing a Processing Surface. Alain J. Martin. Proc. 2nd Caltech Conf. on VLSI,527--537, Jan. 1981. [5047:TR:82]

A Distributed Implementation Method for Parallel Programming. Alain J. Martin. Information Processing 80, S.H. Lavington Ed., pp~309-314, North-Holland, (1980).

An Axiomatic Definition of Synchronization Primitives. Alain J. Martin. Acta Informatica,16, 219--235, 1981. [5046:TR:82]

Two Implementations of the Conditional Critical Region Using a Split Binary Semaphore. Alain J. Martin and J.L.W. Kessels. Information Processing Letters, 67--71, Feb. 1979.

On-the-Fly Garbage Collection: An Exercise in Cooperation. with E.W. Dijkstra et al., Communications of the ACM, 966--975, Nov. 1978. [PDF]

Throughput Optimization of Quasi Delay-Insensitive Circuits via Slack Matching
Piyush Prakash, December 2007. [PDF]

Soft-error Tolerant Quasi Delay-insensitive Circuits
Wonjin Jang, September 2007

Rigorous analog verification of asynchronous circuits
Karl Papadantonakis, December 2005

High-level synthesis and rapid prototyping of asynchronous VLSI systems
Cathering Wong, May 2004

Energy-delay Complexity of Asynchronous Circuits.
Paul Penzes, May 2002. [PS]

Asynchronous Pulse Logic.
Mika Nyström, May 2001. [CSTR:2001.011]

The Impact of Asynchrony on Computer Architecture.
Rajit Manohar, June 1998.

Semantics for VLSI Synthesis.
Marcel van der Goot, May 1995.

A General Approach to Performance Analysis and Optimization of Asynchronous Circuits.
Tak Kwan Lee, May 1995. [CS-TR-95-07]

An Energy Complexity Model for VLSI Computations.
Jose Andres Tierno, January 1995. [CS-TR-95-02].

Testing Delay-Insensitive Circuits.
Pieter Johannes Hazewindus, May 1992. [CS-TR-92-14]

Performance Analysis and Optimization of Asynchronous Circuits.
Steven Morgan Burns, December 1990. [CS-TR-91-01]

A Parallel Execution Model for Logic Programming.
Peyyun Peggy Li, April 1986.

Slack Matching
Piyush Prakash, 2005 [CaltechETD]

Single-event-upset-tolerant Quasi-delay-insensitive Circuits
Wonjin Jang, 2004

What is Deterministic CHP, and is Slack Elasticity That Useful?
Karl Spyros Papadantonakis, 2002. [CaltechETD]

Designing the Port Interface Unit for the Lutonium Asynchronous Microcontroller.
Eino-Ville Talvala, Senior Thesis, Caltech, 2003 [PDF]

Automating the Layout of the Asynchronous 80C51 Microcontroller.
Elaine Ou, Senior Thesis, Caltech, 2003

The CAST Parser.
Matthew S. Hanna, 2000.

Efficient Compilation of Handshaking Programs to Production Rules.
Robert Southworth, 2000.

A Graphical Method for Process Decomposition.
Catherine Grace Wong, 2000.

Gretel: An Interactive Router for Magic.
Eitan Eduardo Grinspun, 1999.

The Design of High-performance Asynchronous Circuits for the Caltech MiniMIPS Processor.
Paul Penzes, 1998.

Pipelined Asynchronous Cache Design.
Mika Nyström, 1997.

On Detection and Generation of Deadlock-free Reshufflings in VLSI Synthesis Method.
Jiazhao Jessie Xu, 1996. [CS-TR-96-10]

Pipelined Asynchronous Circuits.
Andrew Matthew Lines, 1995. [CS-TR-95-21]

Production Rule Verification for Quasi-Delay-Insensitive Circuits.
James N. Cook, 1993. [CS-TR-93-23]

Designing Asynchronous Circuits in Gallium Arsenide.
Jose A Tierno, 1993. [CS-TR-92-19].

Communication Behavior of Linear Arrays of Processes.
Tak K. Lee, 1989. [ | CS-TR-89-13 ]

Comparison of Strict and Non-strict Semantics for Lists.
Jerry R. Burch, 1988. [CS-TR-88-12]

Automated Compilation of Concurrent Programs into Self-timed Circuits.
Steven M. Burns, 1988. [CS-TR-88-02]