CS 181a: VLSI Design Laboratory


CS 181a General Information

Time and Place
Class: Mondays and Wednesdays, 1:00-2:25pm, 243 Annenberg
Optional Homework Recitation: Friday 5 PM, 104 Annenberg

Alain Martin <alain@async> 217 Annenberg

Teaching Assistant
Anjian Wu <awwu@caltech> Avery 145
(Feel free to email or stop by)
Office hours (in 104 Annenberg):

  • Sundays 8:00 PM - 9:30 PM
  • Mondays 9:30 PM - 11:00 PM
Kevin Chen <kchen2@caltech> Avery 142

Office hours (in 104 Annenberg):
  • Sundays 8:00 PM - 9:30 PM
  • Mondays 9:30 PM - 11:00 PM

Chris Moore <cc@async>
Sean Keller <sean@async>
(They don't reply emails to strangers, try not to email them)

Course Secretary
Diane Goodfellow <diane@cs> 246 Annenberg

System Managers
Dave LeBlanc <help@cs> 112 Annenberg

Homework Assignments

Final Project References and Tests

Homework Tests

Recitation Notes


Reference Material

Previous Years

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Catalog Entry
CS 181 ab. VLSI Design Laboratory. 12 units (3-6-3); first, second.

Digital integrated systems design, with projects involving the design, verification, and testing of high-complexity CMOS microcircuits. First-term lecture and homework topics emphasize disciplined design, and include CMOS logic, layout, and timing; computer-aided design and analysis tools; and electrical and performance considerations. Each student is required in the first term to complete individually the design, layout, and verification of a moderately complex integrated circuit. Advanced topics second term include self-timed design, computer architecture, and other topics that vary year by year. Projects are large-scale designs done by teams.