Schedule for queue group week 0 jan 5 group assignments, discuss project proposals week 1 jan 12 discuss design alternatives lab: analyze PascalS programs week 2 jan 19 discuss depth of queues and number of queues lab: verilog intro week 3 jan 26 discuss control, ALU architecture lab: verilog modules for ALU week 4 feb 2 discuss register set lab: verilog modules for parts, prepare presentation week 5 feb 9 CLASS PRESENTATION lab: verilog modules for parts week 6 feb 16 discuss bandwidths / energy lab: assemble components into one working module, week 7 feb 23 discuss refinements lab: simulate programs on module, implement refinements week 8 mar 2 discuss further refinements lab: resimulate programs, prepare presentation week 9 mar 9 CLASS PRESENTATION
If there are students who choose to do that, some students may work concurrently on beter methods of code generation for the pascalS compiler.