Hi All,

Just to make sure that everyone knows what they are
to do this week:

For all your designs (except perhaps some control) stick 
to the following rules:
(0) m3 ONLY vertical
(1) m2 ONLY horizontal, plus keep as many horizontal m2 channels
       open as you can
(2) bit pitch (arrayed height of cells 256 lambda)
(3) Vdd, GND, reset run vertically in m3
(4) Use ONLY reset as power supply (NOT reset_) to keep the
    reset safe
(5) make all transistors so that they can easily be stretched
    by making the cells wider

(6) This is a new one:
    We will leave room for a control cell after every four data cells
    hence our data path will be 40 cells high.

Assignments:

Mengchen & Yushan will make a truly wonderful low forward
latency 4-bit split with copy of the control bit. This will
be a 5 cell unit with the topmost cell being control. They
will use a 5-input C-element for acknowledgement of the control
bit.

Tom Z. & Brian will make a truly wonderful low forward latency
4-bit merge (no copy of the control bit). They will
use a 4-input C-element for acknowledgement of the control
bit.

These two groups will share their designs at the earliest possible
time and try to make progress towards completing a rotate unit
and a 4 to 4 router respectively. (Both 32 bit data.) This part of
the design is somewhat optional, the above two paragraphs are not.

Tom D. will make a nice register cell.      

Greg and Laurent will complete a cell that can perform the separation
of data and instructions as discussed a few classes ago. I think you
cannot simply apply the trick twice to separate data that are addresses
from other data. Think about this, and try to find a solution.
You can assume you will get a good split design from Menchen and Yushan.

Kurt will complete the decomposition of the data memory interface in
terms of cells that we know how to build and a few finite-state machine
like cells. (I know I asked you to do something else in class, do that
if you've already started it, but I think this assignment might be a
little more useful at this point).

Hints:

Don't start SPICE until you are certain the designs are correct. Talk
to Andrew (or Uri or me) if you wonder if your design is safe. Find
good sizes by doing back-of-the-envelope calculations, but most of all
make sure your cells can be resized.

Put the finished cells with a little .doc or .ps file in the cs181q
account so that we can all easily access it, and notify the group
by e-mail when something has been completed.

Help each other as much as possible! I would like to see this weeks
splits and merges be better than any of the ones any of us has
designed so far, and that will happen only if we share our experiences.

-Peter