Asynchronous or "Delay-Insensitive" CMOS

All commercial computers sold today are "synchronous," i.e., the activities of the various parts of the system are synchronized with a centrally generated clock. Furthermore, the internal activities of the central processing unit are also synchronized with a clock. In contrast, the Caltech Asynchronous Microprocessor is entirely asynchronous. It uses no clock, and it is the first such processor ever to be designed. (Today, the ranks of functioning asynchronous processors has swelled to at least two with the development, albeit along a different path from the Caltech processor, of an asynchronous version of the ARM: AMULET.)

I'm going to focus on the power aspect of asynchronous design, since this is what the Potato Processor illustrates. There are two main arguments for low power consumption in asynchronous processors. Since there is no clock, the chip is entirely idle when there is no data, and then it draws very little power. The second reason, which is actually the reason which is most important to us here, is that asynchronous (delay-insensitive) circuits adjust their operating speed to environmental conditions. This is a huge advantage. We don't need to carry out complex trials and statistical guesswork to figure out what voltage and clock speed we should run our chips at in order to leave an appropriate margin. In a clocked system, we would have to adjust the clock to run slower if we turn down the voltage of the power supply.

The self-regulating power supply allows us to operate the delay-insensitive processor from just about any power source that is capable of providing approximately fifty microwatts of power at 0.8 volts. The speed of computation adjusts itself to the amount of power available.

(Continued...)


By Mika Nyström, mika@vlsi.cs.caltech.edu January 16, 1996.