Current Research
I am PhD student in the Department of Computer Science at Caltech, and I'm a member of the Asynchronous VLSI group working under Professor Alain Martin.
We work primarily with Quasi Delay-Insensitive (QDI) asynchronous circuits, and I am currently researching novel computer architectures leveraging asynchronous circuits.
At the moment, I'm exploring the use of run-time reconfigurable architectures tightly coupled with a traditional von Neumann architecture to speedup embedded systems via dynamic optimization in hardware.
Past Research
I architected and designed much of this reconfigurable supercomputer as detailed in my M.S.
Thesis.
Gate/Switch Level Simulation Enhancement
I developed a technique that resulted in an order of magnitude speedup in BDD based gate level circuit simulation - narrowing the gap between RTL and gate level simulation in
Dynamically Optimized Gate-Level Circuit Simulation.
Asynchronous Circuit Design
I designed and spiced a fair arbiter/true random number generator utilizing Johnson noise in
A CMOS Quasi-Delay Insensitive Asynchronous VLSI Random Number Generator.
Papers
Coming Soon.
