An architecture for asynchronous FPGAs.
Catherine G. Wong, Alain J. Martin, and Peter Thomas.
To appear in Proc. IEEE International Conference on Field-Programmable
Technology (FPT'03), December 2003.
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Abstract ::: We present an architecture for a quasi delay-insensitive
asynchronous field-programmable gate array. The logic cell is a complete
asynchronous pipeline stage and the interconnects are entirely delay
insensitive.
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Three generations of asynchronous microprocessors.
Alain J. Martin, Mika Nyström and Catherine G. Wong.
To appear in IEEE Design & Test of Computers, special
issue on Clockless VLSI Design, Nov 2003.
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Abstract ::: Asynchronous VLSI offers low power, modularity, and
robustness to physical variations. We describe three generations of
asynchronous microprocessors designed at Caltech between 1988 and today,
and the evolving circuits and design techniques associated with each of
them.
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High-level synthesis of asynchronous systems by data-driven
decomposition.
Catherine G. Wong and Alain J. Martin.
Proc. 40th Design Automation Conference, June 2003.
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Abstract ::: We present a method for decomposing a high-level
program description of a circuit into a system of concurrent modules that
can each be implemented as asynchronous pre-charge half-buffer pipeline
stages (the circuits used in the asynchronous R3000 MIPS microprocessor).
We apply it to designing the instruction fetch of an asynchronous 8051
microcontroller, with promising results. We discuss new clustering
algorithms that will improve the performance figures further.
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The Lutonium: a sub-nanojoule asynchronous 8051 microcontroller.
Alain J. Martin, Mika Nyström, Karl Papadantonakis, Paul I. Penzes,
Piyush Prakash, Catherine G. Wong, Jonathan Chang, Kevin S. Ko, Benjamin
Lee, Elaine Ou, James Pugh, Eino-Ville Talvala, James T. Tong, Ahmet Tura.
Proc. 9th IEEE International Symposium on Asynchronous Systems &
Circuits, May 2003.
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Abstract ::: We describe the Lutonium, an asynchronous 8051
microcontroller designed for low Et^2. In 0.18-μm CMOS, at nominal
1.8 V, we expect a performance of 0.5 nJ per instruction at
200 MIPS. At 0.5 V, we expect 4 MIPS and
40 pJ/instruction, corresponding to 25,000 MIPS/Watt. We describe
the structure of a fine-grain pipeline optimized for Et^2 efficiency,
some of the peripherals implementation, and the advantages of an
asynchronous implementation of a deep-sleep mechanism.
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Data-driven process decomposition for circuit synthesis.
Catherine G. Wong and Alain J. Martin.
Proc. IEEE Conference on Electronic Circuits and Systems, September
2001.
Speed and energy performance of an asynchronous MIPS R3000 microprocessor.
Alain J. Martin, Mika Nyström, Paul Penzes, and Catherine Wong.
Caltech Computer Science Technical Report CSTR:2001.012. June 2001.
